Colleges and universities
Run VLSI and digital-design labs without a board shortage. Hidden testbenches, attempt limits, deadlines, live results, a similarity report and a CSV gradebook for your records.
SiliconLab Live · RTL in the browser
A real Icarus Verilog simulator and a waveform viewer that run from any browser, with nothing to install. Instructors set auto-graded labs with hidden testbenches and watch results arrive live.
Free during the pilot. Teaching a course? Ask for instructor access after you sign in.
How it works
Edit Verilog and SystemVerilog-2012 in a highlighted editor with multiple files.
Press Run. Icarus Verilog compiles and simulates in a sandbox, usually in under a second.
Zoom and pan the waveform, place a cursor, read values in hex, decimal or binary.
For class labs, submit to a hidden testbench and get per-test marks straight away.
Built for
Run VLSI and digital-design labs without a board shortage. Hidden testbenches, attempt limits, deadlines, live results, a similarity report and a CSV gradebook for your records.
Try an idea quickly, keep saved designs and share reproducible testbenches with your group, all from a browser.
Check an RTL concept, train new engineers on house-style exercises and screen candidates with practical Verilog tasks.
Every simulation runs in an isolated, network-less sandbox with strict time, memory and output limits. Student code never touches your machines.
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