Scope → build → verify → review
From requirements to reviewable results.
Nine project workstreams connect RTL, FPGA, embedded firmware, PCB studies, verification and research media.
These are proposed planning windows from programme start. Tests begin as not run; approval requires actual evidence. Device limits, standards and signoff criteria must be tailored to the project.
Day 0–14
01 · Project charter and requirements
Gate: Requirements baseline
Problem and audience
Define user, use case, target hardware, deliverables and exclusions.
Acceptance: Approved brief names a demonstrable outcome and acceptance owner.
Measurable requirements
Specify behavior, interfaces, throughput, latency, memory and power budgets.
Acceptance: Unique IDs, units, tolerance, source and verification method; TBDs assigned owners.
Verification strategy
Map every requirement to tests, analysis or inspection.
Acceptance: No orphan requirement; acceptance rules documented before execution.
Budget and licensing
Inventory boards, tools, instruments, IP licences and lead times.
Acceptance: Approved budget; tool and IP availability verified.
Review authority
Assign design, verification, quality, security and customer roles.
Acceptance: Reviewers, escalation and change-impact workflow approved.
Day 7–28
02 · Architecture and reproducible toolchain
Gate: Architecture review
Block and interface architecture
Document datapaths, state machines, clocks, resets, buses and register maps.
Acceptance: Interface contracts and reset behavior reviewed by both design and verification owners.
Repository and build baseline
Pin source, dependencies, constraints, test data and build scripts.
Acceptance: Clean checkout reproduces the build with recorded versions and hashes.
Reference model
Build an independent behavioral oracle for expected outputs and error responses.
Acceptance: Normal, boundary and invalid-input examples agree with the written specification.
Static checks
Configure lint, compiler warnings and coding review rules.
Acceptance: No unresolved high-severity finding; waivers have rationale and owners.
Regression automation
Archive deterministic test results, logs and seeds.
Acceptance: Failed checks block promotion; a retained seed reproduces a failure.
Day 21–60
03 · RTL implementation and verification
Gate: RTL verification review
Module functional tests
Test arithmetic, registers, control logic, reset and parameters.
Acceptance: Expected-value checks cover documented boundaries and configurations.
Protocols and backpressure
Exercise legal/malformed sequences, stalls, retries and arbitration.
Acceptance: No loss, duplication or unbounded stall within documented assumptions.
Assertions and formal scope
Define invariants, progress properties and formal assumptions.
Acceptance: Bounds, counterexamples and gaps reviewed; bounded proof is labeled accurately.
Coverage closure
Track requirements, functional scenarios and supported code coverage.
Acceptance: Approved goals met or exclusions signed; coverage alone is not correctness.
Clock and reset domains
Review crossings, synchronization intent and reset release.
Acceptance: Every crossing has handling and review evidence; simulation alone is not CDC signoff.
Day 45–90
04 · FPGA implementation and bench validation
Gate: FPGA acceptance review
Synthesis and resources
Inspect inferred logic, warnings and target utilization.
Acceptance: No unexplained critical warning; resource use fits the approved budget.
Timing closure
Review clocks, delays, exceptions, setup/hold and unconstrained paths.
Acceptance: Required paths constrained and timing meets the approved target and corners.
Pinout compatibility
Cross-check package pins, bank voltages and board interfaces with vendor data.
Acceptance: Peer-reviewed constraints match the actual board revision.
Board functional evidence
Compare known-input/output captures with reference results.
Acceptance: Board serial, bitstream hash and instrument settings retained; discrepancies resolved.
Performance and recovery
Measure latency, throughput, restart and error recovery.
Acceptance: Measured results meet requirements; repeatability and limitations recorded.
Day 30–100
05 · Embedded firmware and board bring-up
Gate: Firmware integration review
Board readiness
Verify assembly revision, BOM, power compatibility and vendor bring-up guidance.
Acceptance: Inspection checklist and authorized bench setup approved.
Peripheral drivers
Test GPIO, UART, SPI, I2C and selected devices or fixtures.
Acceptance: Transactions, invalid responses, timeouts and recovery meet interface contracts.
Firmware test suite
Exercise logic, state transitions, buffer boundaries and concurrency.
Acceptance: Repeatable host and target tests mapped to requirements and versioned builds.
Boot, update and security
Review access control, secret storage, update authenticity and recovery.
Acceptance: Negative tests reject unauthorized operations; recovery verified on an approved target.
Resource and reliability evidence
Measure memory, scheduling, power and long-run behavior.
Acceptance: Project-specific budgets and duration met; resets and data-loss anomalies dispositioned.
Day 50–130
06 · PCB and ASIC design studies
Gate: Manufacturing-data review
PCB electrical and layout checks
Review ERC, DRC, stackup, return paths, interfaces and footprints.
Acceptance: Violations resolved or signed; supplier fabrication constraints confirmed.
Manufacturing package
Prepare BOM, fabrication, assembly, sourcing and traceability records.
Acceptance: Independent review checks file revisions, pin mapping, alternates and supplier needs.
ASIC physical exploration
Use a licensed flow with recorded PDK, libraries and constraints.
Acceptance: Reports retain provenance; educational PDK results labeled as studies.
Signoff applicability
Plan equivalence, corners, DRC/LVS, power integrity and DFT as applicable.
Acceptance: Specialists approve required checks; no tapeout claim without foundry signoff evidence.
Procurement decision
Review uncertainty, costs, supply risk and test access before ordering.
Acceptance: Written release gate with accepted risks, frozen revision and inspection plan.
Day 90–150
07 · System verification and release
Gate: System acceptance review
End-to-end verification
Integrate firmware, FPGA, host tools and interfaces.
Acceptance: Every accepted requirement traces to current evidence or an approved disposition.
Fault and robustness tests
Exercise approved disconnects, invalid data, restart and resource exhaustion.
Acceptance: Recovery meets requirements without undocumented data loss.
Measurement credibility
Record calibration, method, repetitions, uncertainty and raw data.
Acceptance: Conclusions stay within instrument capability and test applicability.
Release and restoration
Prepare manifest, installation, backup and rollback instructions.
Acceptance: Independent install and restore reproduce the accepted configuration.
Customer handover
Deliver source/licences, reports, operating notes and known issues.
Acceptance: Customer accepts scope; limitations and future work remain visible.
Day 120–180
08 · Productization and paid delivery
Gate: Commercial and support review
Fixed-scope offers
Define audit, sprint, verification study and team-lab deliverables.
Acceptance: Written price, stages, exclusions and support terms reviewed.
Purchase and milestone tracking
Link commissioned scope, orders and delivery acceptance.
Acceptance: Payments use verified provider records; completion needs acceptance evidence.
Support and maintenance
Define severity, response targets, ownership and patch cadence.
Acceptance: Sample issue traces through acknowledgement, resolution and retest.
Compliance applicability
Identify market, product category and applicable safety/EMC/privacy obligations.
Acceptance: Qualified reviewers approve obligations; this template is not certification.
Future roadmap
Review defects, schedule, costs and customer feedback.
Acceptance: Next-quarter studies have owners, test goals, scope and provisional deadlines.
Day 0–90
09 · Research videos and social content
Gate: Editorial publication review
Editorial calendar
Plan RTL, FPGA, firmware, PCB and verification explainers for four channels.
Acceptance: Audience, sources, owner, review date and channel targets assigned.
Research and scripts
Link claims to sources and identify simulated versus bench results.
Acceptance: Technical review checks claims, demonstrations and licences.
Accessible video production
Produce readable visuals, captions, thumbnails and commissioned narration.
Acceptance: Rendered video passes factual, visual, caption and rights review.
Publishing and analytics
Connect YouTube and record LinkedIn, Instagram and Facebook ownership.
Acceptance: Publishing access verified; measured engagement tied to platform reports.
Content monetization
Track project enquiries, sponsorships and educational products.
Acceptance: Disclosures and offers approved; measured conversion informs future topics.
Evidence controls the next step
Requirements map to verification cases. Failed or changed evidence reopens affected gates. Risks, owners, deadlines, documents and test reports stay connected to the work. Parallel FPGA, firmware and PCB studies converge at system acceptance.
Tools and references
Commission a fixed-scope project
Agree the deliverables, milestones, evidence and written price before starting. The six browser lab tools remain available for personal planning.